1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, a method for designing semiconductor integrated circuit and a system for designing semiconductor integrated circuit.
2. Description of Related Art
It is known that, when the current is continuously caused to flow through the metal interconnection of the semiconductor integrated circuit, disconnection or resistance degradation of the interconnection takes place depending on phenomenon of metal element transportation called as an electromigration.
When the current is caused to flow through the metal interconnection of the semiconductor integrated circuit, electron of electron flow and metal atoms collide. The electromigration is phenomenon where the metal atoms move in the direction of electron flow while receiving stress caused by momentum exchange on the occasion of the collision between electron of electron flow and metal atoms.
Porosities are accumulated in upstream of the electron flow caused by migration of the metal atom. A large amount of accumulated porosities form a hole called as an optically observable physical void. The void grows in the interconnection. There occurs such problems as electrical conductivity is lost; defect takes place in transmission of signal while increasing interconnection resistance, or the like in the interconnection where the void grows in certain degree of size. Also, it is known that an acceleration factor of this electromigration is current density and atmospheric temperature.
A service life of the interconnection deteriorates caused by the electromigration. In order to compliance with this interconnection life degradation, so far particularly restriction of the drive current has been adopted to cope with the degradation of the service life. As described in paragraph “0002” of the Japanese Laid-Open Patent Publication No. HEI 07-21246, required minimum line width of the conventional interconnection is designed in such a way that the required minimum line width increases directly proportional to the current amount caused to flow.
By applying this concept, an interconnection is formed on a semiconductor substrate with a damascene method. FIG. 3 is one which represents the interconnection width with current caused to flow through this interconnection in every service life of 5 years, 10 years, 15 years and 20 years. From this drawing, for instance, in the case that current of 0.1 mA is caused to flow through the interconnection with interconnection width: W=0.1 μm and the service life: 10 years; so, when current of 0.2 mA is caused to flow through the interconnection, this proves that it is necessary to design width W of the interconnection W=0.2 μm.
The semiconductor integrated circuit, which is designed in such a way as above conventional concept, increases the interconnection width directly proportional to increase of the current caused to flow through the interconnection. Accordingly, when being caused to flow large current, there has been the problem that a chip area becomes large. In particular, when the service life of the interconnection is long and the large current is caused to flow, there is the problem that extremely large chip area is necessary.